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Espressif Systems /ESP32-P4 /PMU /LP_INT_ENA

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Interpret as LP_INT_ENA

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LP_CPU_SLEEP_REJECT_INT_ENA)LP_CPU_SLEEP_REJECT_INT_ENA 0 (_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA)_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA 0 (_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA)_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA 0 (_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA)_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA 0 (_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA)_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA 0 (_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA)_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA 0 (_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA)_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA 0 (_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA)_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA 0 (_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA)_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA 0 (_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA)_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA 0 (_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA)_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA 0 (_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA)_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA 0 (_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA)_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA 0 (LP_CPU_WAKEUP_INT_ENA)LP_CPU_WAKEUP_INT_ENA 0 (SLEEP_SWITCH_ACTIVE_END_INT_ENA)SLEEP_SWITCH_ACTIVE_END_INT_ENA 0 (ACTIVE_SWITCH_SLEEP_END_INT_ENA)ACTIVE_SWITCH_SLEEP_END_INT_ENA 0 (SLEEP_SWITCH_ACTIVE_START_INT_ENA)SLEEP_SWITCH_ACTIVE_START_INT_ENA 0 (ACTIVE_SWITCH_SLEEP_START_INT_ENA)ACTIVE_SWITCH_SLEEP_START_INT_ENA 0 (HP_SW_TRIGGER_INT_ENA)HP_SW_TRIGGER_INT_ENA

Description

need_des

Fields

LP_CPU_SLEEP_REJECT_INT_ENA

need_des
_0P1A_CNT_TARGET0_REACH_0_LP_INT_ENA

reg_0p1a_0_counter after xpd reach target0
_0P1A_CNT_TARGET1_REACH_0_LP_INT_ENA

reg_0p1a_1_counter after xpd reach target1
_0P1A_CNT_TARGET0_REACH_1_LP_INT_ENA

reg_0p1a_0 counter after xpd reach target0
_0P1A_CNT_TARGET1_REACH_1_LP_INT_ENA

reg_0p1a_1_counter after xpd reach target1
_0P2A_CNT_TARGET0_REACH_0_LP_INT_ENA

reg_0p2a_0 counter after xpd reach target0
_0P2A_CNT_TARGET1_REACH_0_LP_INT_ENA

reg_0p2a_1_counter after xpd reach target1
_0P2A_CNT_TARGET0_REACH_1_LP_INT_ENA

reg_0p2a_0 counter after xpd reach target0
_0P2A_CNT_TARGET1_REACH_1_LP_INT_ENA

reg_0p2a_1_counter after xpd reach target1
_0P3A_CNT_TARGET0_REACH_0_LP_INT_ENA

reg_0p3a_0 counter after xpd reach target0
_0P3A_CNT_TARGET1_REACH_0_LP_INT_ENA

reg_0p3a_1_counter after xpd reach target1
_0P3A_CNT_TARGET0_REACH_1_LP_INT_ENA

reg_0p3a_0_counter after xpd reach target0
_0P3A_CNT_TARGET1_REACH_1_LP_INT_ENA

reg_0p3a_1_counter after xpd reach target1
LP_CPU_WAKEUP_INT_ENA

need_des
SLEEP_SWITCH_ACTIVE_END_INT_ENA

need_des
ACTIVE_SWITCH_SLEEP_END_INT_ENA

need_des
SLEEP_SWITCH_ACTIVE_START_INT_ENA

need_des
ACTIVE_SWITCH_SLEEP_START_INT_ENA

need_des
HP_SW_TRIGGER_INT_ENA

need_des

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data